[1]
D. M. Rifqie, Y. A. Djawad, F. A. Samman, A. S. Ahmar, and M. M. Fakhri, “Design of Quantized Deep Neural Network Hardware Inference Accelerator Using Systolic Architecture”, J. Appl. Sci. Eng. Technol. Educ., vol. 6, no. 1, pp. 27–33, Jun. 2024.